The quest to develop smaller and smaller dynamic random access memory (DRAM) cells and related structures is a well-known goal. In integrated circuit manufacturing, certain costs are relatively fixed no matter what integrated circuit is fabricated. Thus, the greater density of memory on a single integrated circuit provides greater economy on a per bit basis by spreading these fixed costs across more memory capacity. In addition, greater memory storage capacity allows greater memory capacity of the end user products, such as computers, in a smaller package. Therefore, the value to the customer is increased. Because 50% or more of the area of a DRAM is used for memory cells themselves, reduction of the memory cell size allows for far greater numbers of those memory cells to be placed on the DRAM.
Several techniques have been developed to try to reduce the size of memory cells. For example, the fundamental dynamic random access memory cell has been reduced to a minimum of components, i.e. a transistor and a capacitor connected to the source of the transistor. The transistor allows access to the charge stored on the capacitor and the stored charge represents data. The first step in reducing the size of DRAM cells was the effective integration of the transfer transistor and the capacitor. An example of this is found in Kuo, "Random Access Memory Cell with Different Capacitor and Transistor Oxide Thickness", U.S. Pat. No. 4,240,092, issued Dec. 16, 1980 and assigned to the assignee of this application. Kuo is an example of a "Hy-C" cell. As the density of DRAMs increased, limitations of the Hy-C cell became apparent. In order to provide accurate data storage and retrieval, the capacitance of the storage capacitor must be as large as possible. However, the capacitance of the storage capacitor is directly proportional to the area between the plates of the capacitor. In a planar capacitor cell, like the Hy-C cell, this creates a fundamental tradeoff between cell size and cell capacitance.
In order to minimize the surface area occupied by the memory cell while maintaining adequate storage capacitor capacitance, vertical capacitor structures were developed. An example of such a structure is found in Sunami, "Cell Structures for Featured DRAMs", International Electron Devices Meeting Technical Digest (1985), Paper 29.1, pages 694-697. In some cases, the capacitor is formed on a trench etched into the surface of the substrate. An example of this can be found in Ishiuchi, et al., "Submicron CMOS Technologies for 4 Megabit Dynamic RAM", International Electron Devices Meeting Technical Digest (1985), Paper 29.4, pages 706-709. In other cases, a stacked or multiple plate concept providing a vertically stacked capacitor was investigated. An example of this can be found in Sunami, et al., supra.
The difficulties of forming the storage capacitor in a trench have introduced a great deal of complexity into the fabrication of the DRAM cells. For example, see Baglee, et al., U.S. Pat. No. 4,721,987, "Trench Capacitor Process for High Density Dynamic RAM", issued Jan. 26, 1988 and assigned to the assignee of this application. Although the storage capacitor itself has been made smaller, the additional difficulties in connecting the transfer transistor to the capacitor have introduced requirements for spacing tolerances and increased complexity in leakage components. These have all necessitated complex processing steps and additional area occupied to fabricate the DRAM cells.